Verilog/VHDL Design 資深工程師

* Design and develop RTL for Big Data platform.
* Defines and documents RTL changes required for emulation/FPGA.
* Tests and debugs the emulation/FPGA model and collaterals.
* Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform.

Must Have:
* A Bachelors or Masters degree in Electrical Engineering, Computer Engineering or equivalent
* A minimum of 2 years of relevant industry experience.
* System Verilog/Verilog/VHDL coding experience
* Enthusiastic about working at a start-up company

Nice to have:
* Altera or Xilinx FPGA design background
* Real time C/C++ development and debug tools
* Extensive synthesis and simulation skills with professional grade tools
* Proficient at debug of high speed logic designs using sophisticated test equipment
* QPI/PCIe/CAPI/CCIX/Gen-Z knowledge
* Knowledge of ASIC design
* Knowledge of CPU/GPU/DDR/SAS/SATA technology
* Python script development experience
* Exposure to revision control systems
* Excellent written and verbal communication skills
* Big data or Hadoop knowledge

• 績效獎金、定期調薪
• 彈性工時
• 無上限零食
• 創新開放的工作環境
• 培訓課程、職涯規劃、多方位專長培養
• 實習生表現優良直接轉正職，畢業即就業
• 符合勞基法之勞健保、6%勞退
• 週休二日
• 慶生下午茶會