* Design and develop RTL for Big Data platform.
* Defines and documents RTL changes required for emulation/FPGA.
* Tests and debugs the emulation/FPGA model and collaterals.
* Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform.
Must Have:
* A Bachelors or Masters degree in Electrical Engineering, Computer Engineering or equivalent
* A minimum of 2 years of relevant industry experience.
* System Verilog/Verilog/VHDL coding experience
* Enthusiastic about working at a start-up company
Nice to have:
* Altera or Xilinx FPGA design background
* Real time C/C++ development and debug tools
* Extensive synthesis and simulation skills with professional grade tools
* Proficient at debug of high speed logic designs using sophisticated test equipment
* QPI/PCIe/CAPI/CCIX/Gen-Z knowledge
* Knowledge of ASIC design
* Knowledge of CPU/GPU/DDR/SAS/SATA technology
* Python script development experience
* Exposure to revision control systems
* Excellent written and verbal communication skills
* Big data or Hadoop knowledge
• 績效獎金、定期調薪
• 彈性工時
• 無上限零食
• 創新開放的工作環境
• 培訓課程、職涯規劃、多方位專長培養
• 實習生表現優良直接轉正職,畢業即就業
• 符合勞基法之勞健保、6%勞退
• 週休二日
• 慶生下午茶會
請輸入註冊用 email,我們將寄重新修改密碼的連結給你
我們已經寄重新修改密碼的連結至
如果幾分鐘內沒收到信,請再試一次
或寫信給 YOURATOR 客服小幫手
沒收到認證信?請透過下列步驟重新寄送。
我們已經重新寄送驗證信至
如果幾分鐘內沒收到信,請再試一次
或寫信給 YOURATOR 客服小幫手
註冊 Yourator 後您將可以應徵職缺、查詢應徵紀錄與寄送給公司的客製化訊息!
註冊 Yourator 會員後您將收到會員電子報,接收新創媒合會、分享會等活動資訊與閱讀會員限定文章!
在登入後您將可以看到每份工作的相關職缺,讓你找到更多適合你的職缺!
Yourator 團隊將持續開發新功能, 帶給會員更豐富的求職體驗!